Recently, there has been an increasing demand for liquid crystal display devices for use in large-screen liquid crystal TV sets as well as for use in portable telephones (such as mobile phones or cellular phones), notebook PCs, and monitors. As these liquid crystal display devices, an active matrix driving liquid crystal display device capable of performing high-definition display is employed. First, referring to FIG. 11, a typical configuration of the active matrix driving liquid crystal display device will be outlined. FIG. 11 schematically shows a main configuration connected to a pixel in a liquid crystal display unit, using an equivalent circuit.
Generally, a display unit 960 of the active matrix driving system liquid crystal display device includes a semiconductor substrate, an opposing substrate, and a liquid crystal sealed in between these two substrates by opposing these two substrates. On the semiconductor substrate, transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are arranged in a matrix form (of 1280×3 pixel rows×1024 pixel columns in the case of a color SXGA panel, for example). One transparent electrode 967 is formed on an entire surface of the opposing substrate.
Turning ON and OFF of a TFT 963 having a switching function is controlled by a scan signal. When the TFT 963 is turned on, a gray scale signal voltage corresponding to a video data signal is applied to a corresponding pixel electrode 964. Transmittance of the liquid crystal is changed by a potential difference between each pixel electrode 964 and the opposing substrate electrode 967, and even after the TFT 963 has been turned off, the potential difference is held by a liquid crystal capacitor 965 and an auxiliary capacitor 966 for a certain period, thereby displaying an image.
On the semiconductor substrate, data lines 962 and scan lines 961 are wired in the form of a grid (in which 1280×3 data lines and 1024 scan lines are arranged in the case of the color SXGA panel described above). A data line 962 sends a plurality of level voltages (gray scale signal voltages) applied to each pixel electrode 964, and a scan line 961 sends the scan signal. Due to a capacitance produced at an intersection between each of the scan lines 961 and each of the data lines 962 and a liquid crystal capacitance sandwiched between the semiconductor substrate and the opposing substrate, the scan lines 961 and the data lines 962 have become a large capacitive load.
The scan signal is supplied to a scan line 961 from a gate driver 970, and a grayscale signal voltage is supplied to each pixel electrode 964 from a data driver 980 through a data line 962. The gate driver 970 and the data driver 980 are controlled by a display controller 950. A clock CLK, a control signal, and a supply voltage that are necessary are supplied from the display controller 950 to each of the gate driver 970 and the data driver 980, and video data is supplied to the data driver 980. Currently, digital data has become the mainstream of the video data.
Rewriting of data of one screen is performed in one frame period (of approximately 0.017 seconds, usually). Data is successively selected every pixel row (every line) by each scan line, and a gray scale voltage signal is supplied from each data line within a selection period.
While the gate driver 970 should supply the scan signal of at least binary values, the data driver 980 needs to drive a data line by the gray scale voltage signal of multi-valued levels corresponding to the number of gray scales. For this reason, the data driver 980 includes a digital-to-analog converter circuit (DAC) comprising a decoder that converts the video data to an analog voltage and an output amplifier that amplifies the analog voltage and outputs the amplified analog voltage to a corresponding data line 962.
FIG. 12A shows a configuration in which an output buffer of the data driver 980 in FIG. 11 is connected to the data line 962. An output switch SW10 is provided between an output end N9 of an output buffer 90 and a driver output terminal P09 to which the data line 962 is connected. The output switch SW10 is generally provided at the data driver of the liquid crystal display device in order to prevent transition noise induced within a circuit such as the decoder at a time of change in video data from being transmitted to the data line.
FIG. 12B is a graph showing a control signal S1 that controls turning on/off of the output switch SW10 and a state of the switch SW10. Referring to FIG. 12B, a period T1 and a period T2 are provided in one data period. During the period T1 from a start of the one data period, the output switch SW1 is turned off, and transmission of an output signal of the output buffer 90 to the data line 962 is cut off. Then, in the period T2, the output switch SW10 is turned on, and an output signal of the amplifying circuit (amplifier circuit) 90 is output to the data line. The period T1 is set to a period in accordance with a convergence time of the transition noise.
As the output buffer in FIG. 12A, an amplifier circuit having a well-known voltage follower configuration may be employed. The amplifier circuit 90 in FIG. 12A includes a current source M15 which has a first terminal connected to a low voltage power supply VSS, a differential pair formed of N-channel transistors (N-channel MOS transistors) M11 and M12 which have coupled sources connected to a second terminal of the current source M15, a current mirror which is composed of P-channel transistors (P-channel MOS transistors) M13 and M14 connected between an output pair of the differential pair (M11, M12) and a high voltage power supply VDD, a P-channel transistor M16 which has a gate connected to an output terminal node N12 of the current mirror (M13, M14), a source connected to the high voltage power supply VDD, and a drain connected to the amplifier output terminal N9, and a current source M17 which is connected between the low voltage power supply VSS and the amplifier output terminal N9. In this specification, a differential pair formed of transistors Ma and Mb is expressed by a differential pair (Ma, Mb). A current mirror formed of transistors Mc and Md is expressed by a current mirror (Mc, Md).
In the amplifier circuit 90, an inverting-input terminal (a gate of the transistor M11) of the differential pair (M11, M12) is connected to the amplifier output terminal N9. A voltage Vin selected by the decoder (not shown) is supplied to a non-inverting input terminal (a gate of the transistor M12) of the differential pair (M11, M12, according to video data.
Between the gate (node N12) of the P-channel transistor M16 and the drain (amplifier output terminal N9) of the P-channel transistor M16, a phase compensation capacitor C1 and a zero compensation resistor R1 are connected in series. By inserting the zero compensation resistor R1 in series with the phase compensation capacitor C1, zero is created in a frequency characteristic, a band is improved, and a phase margin is increased, thereby stabilizing an operation of the amplifier. This arrangement is effective for reducing a capacitance value (accordingly a size) of the phase compensation capacitor C1 with an area thereof within a chip being comparatively large.
The output switch SW10 that is ON/OFF controlled by the control signal S1 is connected between the amplifier output terminal N9 of the amplifier circuit 90 and the data line 962.
The number of the amplifier circuits 90 provided at the data driver 980 in FIG. 11 corresponds to the number of outputs. Thus, it is important to configure the amplifier circuit 90 with a saved area in a multi-output data driver LSI, in order to achieve cost reduction.
FIG. 13 is a diagram showing another configuration of an amplifier that can be used as the amplifier circuit 90 in FIG. 12A. FIG. 13 is the diagram showing a configuration of an AB-class output circuit disclosed in Patent Document 2 listed later. Referring to FIG. 13, an output stage of this AB-class output circuit includes a P-channel transistor M85 connected between a high voltage power supply VDD and an output terminal Vout and an N-channel transistor M86 connected between the output terminal Vout and a low voltage power supply VSS. The output stage is equipped with high charging and discharging capabilities for the output terminal Vout. A gate NP1 of the P-channel transistor M85 is connected to an output terminal of a driver 89 that receives an input signal Vin, and performs a charging operation of an output Vout of the amplifier. A change in the input signal Vin is transferred to a gate NN1 of the N-channel transistor M86 via an intermediate stage (M81, M82), and the N-channel transistor M86 performs a discharging operation of the output Vout of the amplifier.
The intermediate stage includes a P-channel floating current source M81 and an N-channel floating current source M82, and current sources M83 and M84. Bias voltages BP8 and BN8 are supplied to gates of the p-channel floating current source M81 and the N-channel floating current source M82, respectively, and the P-channel floating current source M81 and the N-channel floating current source M82 are connected between the gates (NP1, NN1) of the transistors M85 and M86. The current source M83 is connected between the high voltage power supply VDD and the gate NP1 of the P-channel transistor M85. The current source M84 is connected between the low voltage power supply VSS and the gate NN1 of the N-channel transistor M86. A sum of currents of the floating current sources M81 and M82 is set to be substantially equal to a current of each of the current sources M83 and M84.
An operation of the AB-class output circuit in FIG. 13 will be described below. When a potential at the terminal NP1 changes to low in response to an input voltage Vin, the P-channel transistor M85 performs the charging operation. Immediately after the change at the terminal NP1, a current of the N-channel floating current source M82 does not change. However, a current of the P-channel floating current source M81 is reduced. Thus, a potential at the terminal NN1 changes to low, so that the discharging operation of the N-channel transistor M86 is stopped. For this reason, the AB-class output circuit in FIG. 13 can perform the charging operation at high speed. When the potential at the terminal NN1 changes to low, the current of the N-channel floating current source M82 begins to increase. Thus, the potential at the terminal NN1 gently rises again after having changed to low temporarily, and becomes close to a potential in a steady state.
On the other hand, when the potential at the terminal NP1 changes to high according to the input voltage Vin, the charging operation of the P-channel transistor M85 is stopped. Though the current of the N-channel floating current source M82 does not change immediately after the change at the terminal NP1, the current of the P-channel floating current source M81 increases. Thus, the potential at the terminal NN1 changes to high, so that the N-channel transistor M86 performs the discharging operation. For this reason, the AB-class output circuit in FIG. 13 can perform the discharging operation at high speed.
When a relationship between the sum of the currents of the floating current sources M81 and M82 and the current of each of the current sources M83 and M84 is maintained with respect to an idling current (a static consumption current) of the intermediate stage, a current value of each of the current sources can be sufficiently reduced.
When the amplifier circuit 90 in FIG. 12A is compared with the AB-class output circuit in FIG. 13, discharging capability of the amplifier circuit 90 in FIG. 12A depends on a current value of the current source M17. In order to implement a high-speed discharging operation, the current value of the current source M17 must be increased.
On contrast therewith, though the current flows through the floating current sources M81 and M82 and the current sources M83 and M84 in the intermediate stage of the AB-class output circuit in FIG. 13, a value of the current that flows through floating current sources M81 and M82 and the current sources M83 and M84 is sufficiently small. The high-speed discharging operation is therefore possible even if the current value is particularly increased. That is, the AB-class output circuit in FIG. 13 is suitable when a display panel with a large load capacitance is driven with lower power consumption.
Though the phase compensation capacitor and the zero compensation resistor are not written down in the AB-class output circuit in FIG. 13, a series circuit of the phase compensation capacitor C and the zero compensation resistor R1 may be connected between the output node NP1 (gate of the P-channel transistor M85) of the driver 89 and the output terminal Vout, for use.
FIG. 14 is a diagram showing a configuration of an operational amplifier in Patent Document 2, which will be listed below. In the configuration in FIG. 14, in order to cause the operational amplifier to perform a stable operation in two different gain states, on-off control is performed over a switch S1 connected in series with a phase compensation capacitor C1 and a switch S2 connected in series with a phase compensation capacitor C4, thereby switching a capacitance value of each of the phase compensation capacitors according to each of the states. By switching a value of each of the capacitors according to each of the two different gain states, the operational amplifier is stably operated in each of the states.
[Patent Document 1]
JP Patent Kokoku Publication No. JP-B-6-91379 (FIG. 1)
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-61-296805 (FIG. 1)